Integrated circuits such as microprocessors, digital signal processors, microcontrollers, memory devices, and the like typically contain millions of Insulated Gate Field Effect Transistors (IGFET's). Because of the desire to lower manufacturing costs and increase circuit speed, integrated circuit manufacturers shrink the sizes of the IGFET's making up an integrated circuit so that more integrated circuits can be manufactured from a single semiconductor wafer. Although the smaller transistors are capable of operating at increased speeds, secondary performance factors such as decreased source-drain breakdown voltage, increased gate current, and instability of the threshold voltage negatively impact transistor performance. Collectively, these adverse performance effects are referred to as short channel effects.
Typical techniques for mitigating short channel effects rely on adjusting the electric field in the channel region to minimize the peak lateral electric field of the drain depletion region. One technique for lowering the lateral electric field is to include source and drain extension regions in the transistor. FIG. 1 is a cross-sectional side view of a transistor 10 having source and drain extension regions. What is shown in FIG. 1 is a cross-sectional view of transistor 10 comprising a silicon substrate 12 having a major surface 14 and a gate structure 16 disposed thereon. Gate structure 16 has opposing sides 22 and 24 and is comprised of a gate conductor 20 stacked on a gate oxide 18. A source extension region 26 extends into silicon substrate 12 and under gate structure 16 and a drain extension region 28 extends into silicon substrate 12 and under gate structure 16. Spacers 32 and 34 are formed along sides 22 and 24 of gate structure 16. Source and drain regions 36 and 38 extend into silicon substrate 12 and are laterally spaced apart from gate structure 16. The drain extension region reduces the maximum electric field in the drain region of transistor 10, thereby reducing the number of hot carriers injected into gate oxide 18. Although the reduction in hot carriers into gate oxide 18 is beneficial, thin gate oxides used in present day high performance CMOS devices still result in high gate-to-drain tunneling current that decreases the performance of the transistor and, thus, the circuits that incorporate the transistors.
Accordingly, what is needed is a semiconductor component having a lowered gate-to-drain tunneling current and a method for manufacturing the semiconductor component.